A typical DRAM cell includes a transistor and a storage capacitor. In the early DRAM cells, storage capacitors of the planar type were used which require the use of large wafer real estate. In recent years, as the size of IC device is continuously miniaturized when smaller chips are made and more devices are packed into a chip, the circuit density on the chip increases to such an extent that the specific capacitance of a storage capacitor must be increased in order to meet such demand. Since chip real estate is limited, the only feasible way of increasing the specific capacitance of a storage capacitor is to increase it three-dimensionally, i.e., to grow the capacitor cell in the vertical dimension and forming a stacked capacitor.
A stacked capacitor can be built on top of a transistor thus allowing a smaller cell to be built without losing the specific capacitance of the cell. It has become a popular design for use in modem semiconductor memory devices to save chip real estate. Other approaches in increasing the cell capacitance, such as the one that involves the formation of a deep trench for storing charges vertically requires complicated processing steps and thus is difficult to carry out.
In modern memory cells, where smaller dimension and higher specific capacitance are desirable characteristics, a DRAM capacitor can be formed by two layers of a semi-conducting material and one layer of a dielectric material sandwiched thereinbetween. A suitable dielectric material utilized in such a capacitor includes a thin oxide layer or a composite oxide-nitride-oxide layer that is sandwiched between two semi-conducting layers of polysilicon for forming the capacitor cell. The capacitor is frequently formed over a bit line on the surface of a silicon substrate.
A typical 16-Mb DRAM cell is shown in FIG. 1. The DRAM cell 10 has a stacked capacitor 20 built on top. The formation of the DRAM cell 10 can be accomplished by first using standard CMOS fabrication steps to form a transistor and to provide a gate oxide layer (not shown). A word line 12 is then formed by first depositing a polysilicon layer of approximately 2500 .ANG. and then doping the polysilicon with phosphorous. A thick layer of insulating material 16 such as TEOS (tetraethoxy silicate) oxide of approximately 3,000 .ANG. is then deposited on top of the first polysilicon layer. By using a standard photomasking process, the two layers are defined and etched by a plasma etching technique. After LDD implants are made in the silicon substrate, oxide spacers are formed on the polysilicon gate structure by depositing a thick layer of TEOS oxide of approximately 2,000 .ANG. and etching in a plasma process. Gates 12 and 14 are thus formed and covered by a thick oxide insulating layer 16. A source and drain mask is then applied to carry out an ion implantation process for forming the source and drain regions in the silicon substrate.
In the next fabrication step, photomasking is used to form openings for the cell contact and plasma etching is used to remove any native oxide layer on the silicon substrate. A second polysilicon layer 22 of approximately 3,500 .ANG. is then deposited and patterned by a photomask to form the lower electrode of the stacked capacitor 20. A dielectric layer 24 of a composite film of oxide-nitride-oxide (ONO) is deposited as the dielectric layer for the capacitor. The total thickness of the ONO composite film is approximately 70 .ANG.. The ONO composite film can be formed by using a thin layer of native oxide as the first oxide layer, depositing a thin nitride layer on top and then oxidizing the nitride layer to grow a top oxide layer. To complete the fabrication of the stacked capacitor, a third polysilicon layer 24 of approximately 2,000 .ANG. thick is deposited on top of the dielectric layer and then doped and patterned by a photomask to form an upper electrode. After the formation of the stacked capacitor, peripheral devices can be formed by masking and ion implantation, followed by the formation of a bit line 28 of a polysilicon/metal silicide material. A thick insulating layer 32 of BPSG or SOG is then deposited over the capacitor and reflowed to smooth out the topography and to reduce the step height. Other back-end-processes such as metallization to form metal lines 34 are used to complete the fabrication of the memory device 10.
The stacked capacitor 10 shown in FIG. 1 has been successfully used in 16 Mb DRAM devices. However, as device density increases to 256 Mb or higher, the planar surface required for building this type of conventional stacked capacitors becomes excessive and must be reduced.
Others have proposed a technique of forming DRAM stack capacitors by using a rugged polysilicon layer as the lower electrode in a capacitor cell. This is shown in FIG. 2 wherein a semiconductor substrate 40 is presented which has a layer of a non-doped silicate glass 42 deposited on top. After the insulating layer 42 is patterned and etched in a conventional etching process, the substrate area 44 is exposed as the storage node capacitor cell contact. In the next processing step, a layer of polysilicon 46 is deposited and formed. The thickness of the polysilicon layer 46 is in the range between 400 .ANG. and 600 .ANG.. To increase the surface area of the polysilicon layer, a rugged surface polysilicon layer 48 is deposited at a relatively low deposition temperature of between 500.degree. C. and 600.degree. C. by a chemical vapor deposition technique. The deposition temperature of the rugged polysilicon must be kept low in order to maintain the wave-like surface texture of the rugged polysilicon. The thickness of the rugged polysilicon layer 48 is between 700 .ANG. and 1000 .ANG.. In a subsequent process, the polysilicon layer 46 and the rugged polysilicon layer 48 are patterned and etched to form a lower electrode of the capacitor cell. A second insulating layer, preferably of an oxide or an oxide-nitride-oxide insulating layer 50 is deposited by a chemical vapor deposition technique. After the second insulating layer 50 is patterned and etched to form a conformal layer on the capacitor cell, a final layer 52 of polysilicon is deposited by chemical vapor deposition and formed as the upper electrode in the capacitor cell.
A storage capacitor that has improved storage capacity can be fabricated by this process. However, the fabrication process is complicated based on the need for a low temperature process to form the rugged polysilicon layer. In a capacitor cell that incorporates rugged polysilicon, the device must not be subjected in a down-stream fabrication step, to a process temperature of higher than approximately 600.degree. C. The high temperature would render the wave-like textured surface of the rugged polysilicon smooth and as a consequence, make it lose its increased storage capacity.
It is therefore an object of the present invention to provide a method for forming a DRAM capacitor that has improved storage capacity without the drawbacks or shortcomings of the conventional method.
It is another object of the present invention to provide a method for forming a DRAM capacitor that has improved storage capacity that does not require the formation of a low temperature rugged polysilicon layer as the lower electrode of the capacitor.
It is a further object of the present invention to provide a method for forming a DRAM capacitor that has improved storage capacity by first depositing an oxide layer on a polysilicon lower electrode layer and then forming an uneven top surface on the oxide layer.
It is another further object of the present invention to provide a method for forming a DRAM capacitor that has improved storage capacity by first depositing an oxide layer on a lower polysilicon layer, forming an uneven top surface on the oxide layer and then anisotropically etching the oxide layer and the polysilicon layer together such that the uneven top surface of the oxide layer is reproduced on the top surface of the polysilicon layer.
It is yet another object of the present invention to provide a method for forming a DRAM capacitor that has improved storage capacity by forming an uneven top surface in a lower polysilicon electrode layer consisting of grooves adjacent to each other such that the surface area of the electrode is increased.
It is still another object of the present invention to provide a method for forming a DRAM capacitor that has improved storage capacity by first depositing an oxide layer on a lower polysilicon electrode layer and then forming an uneven top surface on the oxide layer by a mechanical polishing method utilizing a diamond polishing disk.
It is still another further object of the present invention to provide a DRAM capacitor that has improved storage capacity by forming an uneven top surface on a lower polysilicon electrode layer that consists of grooves juxtaposed to each other wherein the grooves have a depth of at least 500 .ANG..
It is yet another further object of the present invention to provide a DRAM capacitor that has improved storage capacity which incorporates a lower polysilicon electrode layer that has an uneven surface consisting of grooves such that the surface area of the lower electrode layer is increased to improve its charge capacitance.